Pseudorandom bit sequences, also known as chain codes or shift register codes, are employed in various fields, including the synthesis of noise for audio applications, cryptography, and position encoding. In the latter, a pseudorandom sequence is embedded in the scale or disk of a linear or rotary encoding apparatus in the form of a capacitive, magnetic, or optical pattern representing the digital ones and zeroes of the sequence.
The encoder also includes a read station utilizing the appropriate sensing technology to transduce the pattern into digital electrical signals which change as the disk or scale moves in a guided manner relative to it. The total number of discrete positions encoded around the disk, or the number of positions per unit length encoded on a scale, determine the angular or linear resolving power of the encoder. In rotary encoders especially, the number of encoded positions per turn and the fraction of a revolution each position occupies are interchangeably termed the "resolution" of the encoder.
Although the seemingly random electrical output taken directly from such an encoder may be adequate, with the help of a digital correlator, to identify a limited number of special positions (as would a cam, for example), this is not a convenient output format for general use. More commonly, an encoder's output is used to measure angular or linear displacement by subtracting an initial position value from an ending value. By subsequent calculations performed on a series of timed readings, the velocity and acceleration of the motion input being monitored by the encoder may also be computed. Therefore, in order to support typical measurement and control functions, a decoder circuit or program is almost always required to translate the encoder's pseudorandom output into a conventional binary representation.
In accordance with the basic theory of pseudorandom sequences, to perform this translation the decoder determines the monotonic numerical positions of N bit (overlapping, hence "chain" encoded) tags within the sequence embedded in the disk or scale of the encoder, and reports them to a host system. Each N bit tag is unique, thereby indicating the position of the encoder's input mechanism absolutely. This is unlike the method of incremental encoding, which does not encode each position with a unique pattern and therefore reports position information by accumulating counts relative to a starting position or counting register value.
Various types of chain code decoders have previously been used. One example of a decoder is described in U.S. Pat. No. 4,009,377, issued to Elms on Feb. 22, 1977, which is hereby incorporated herein by reference in its entirety. In Elms, the decoder is a circuit which includes a simple bidirectional shift register capable of serially receiving bits of the chain code from two sensors positioned at a linear or angular separation along the code track of the encoder equal to N chain code bits. These two sensors enable bits of the code to be shifted into the register from either direction (depending on the motion of the encoder's disk or scale), such that once the register is loaded in response to an initializing motion of the encoder, changes in the direction of motion resulting in the loss of a data bit at the trailing end of the register are automatically compensated by the shifting in of a new bit at its leading end. Thus a full N bit tag is always maintained in the shifter, available for decoding, despite direction reversals.
However, this method of acquiring the chain code data from the encoder makes the encoder unnecessarily complicated and interferes with retrofitting a chain code track in place of a standard index code track in existing incremental encoder designs. Specifically, the use of two indexing sensors in the encoder inflicts one of two drawbacks. A specially tooled detector pair and/or aperture mask is provided for each and every resolution offered in a given encoder design to accommodate its unique cumulative dimension for N bits. Otherwise, a duplicate parallel or concentric chain code track is provided at a different enough concentric radius or parallel displacement, and perhaps also skewed with respect to the first, so as to permit conventionally dimensioned and mounted sensors to achieve an apparent N bit displacement from one another, as though they were reading from the same track.
In opposition to the inconvenience of its physical implementation within the encoder and the obstacle that presents to retrofitting earlier incremental designs, it is a somewhat counterbalancing advantage of the dual index sensor approach that the bidirectional shift register it accumulates tags with has a simple and elegant construction. Furthermore, if one or more direction reversals occur during the acquisition of the initial code tag from the encoder, a net traverse of only N total bits suffices to fill it, and as described above, subsequent motions may include any number and spacing of direction reversals without producing ambiguity in the code tags acquired en route. Nevertheless, electronic design elegance has little value and digital complexity little cost, when contrasted with the expenses related to extra code tracks, extra sensors, and specially tooled aperture masks and sensor mounting methods. It is therefore desirable to devise a method for serially accumulating the chain code tag within the decoder which, though more electronically complex, obviates the need for a second index sensor in the encoder and still fully minimizes to N bits the initialization angle or distance to be traversed. Elms suffers a further disadvantage that, even though its tag accumulator is suited to minimizing the initialization traverse when the encoder is "wiggled" bidirectionally at the start, the control logic of its decoder initiates the decoding process only when a full N bits have been traversed in one direction or the other. Thus its worst case initialization traverse is 2N bits.
When a full initial code tag is acquired following power up of the encoder/decoder system, the decoder translates the tag into some conventional binary absolute position format. In Elms, the decoding process is accomplished by separately synthesizing within the decoder the same pseudorandom sequence embedded in the encoder's disk or scale. Sequentially synthesized tags are compared to the initial encoder tag maintained in the shift register. When a match is found, a counter indicates the absolute position of the initial tag within the sequence thus discovered. Further motion of the encoder produces changes in the code tag from the encoder which are "tracked" by the decoder's synthesizer, which is capable of both forward and reverse synthesis in order to follow bidirectional encoder motions. This decoding system generally follows the operational principles of other tracking analog to digital converters, which, though they do not employ pseudorandom techniques, are often chosen for their efficiency in applications that do not involve analog inputs having discontinuous behavior.
A further disadvantage of Elms is that the length of the pseudorandom sequence, and therefore the encoding resolution, is limited to schemes having one count short of the full binary complement (2.sup.N -1). Elms' sequences are commonly known as "maximal length" sequences, or m-sequences. Thus, the resolutions capable with such an encoder/decoder system have been quite inflexible whenever the encoded scale could not simply be truncated to eliminate undesired working length. Such is always the case with rotary encoders, which require the pseudorandom sequence to form a closed loop where all N bit tags retain their uniqueness to avoid decoding ambiguity, even those spanning the join between a sequence's "end" and "beginning". Furthermore, it is quite common that the resolution of a common incremental rotary encoder, particularly, will be selected based on a requirement that it read out in decimal degrees, or that it perform an English to Metric conversion when used with a pulley or gear of a certain circumference, or that it supply an exact binary number of measuring steps per revolution to simplify subsequent digital calculations, et cetera. If possible, chain code encoders ought to be allowed by the design of their corresponding decoders to offer these same capabilities.
Other decoders have been more flexible in the resolutions that they support, but these decoders do not synthesize pseudorandom sequences. Instead, they use look-up tables, wherein the conventional monotonic binary positions are stored at N bit addresses which are ordered to correspond with the N bit code tags of the pseudorandom sequence. Look-up tables may be contained in the non-volatile storage memory of a microprocessor or computer, or embodied in a dedicated PROM (programmable read only memory). Decoders employing these techniques disadvantageously require memory which may be substantial, depending on the desired resolution. They are also unacceptably slow for supporting contemporary encoding velocities (typically 400,000 quadrature states per second read from the encoder disk or scale, and up to 10 times that many) when depending on a microprocessor for their operation, or too unsophisticated in their operating modes and features when utilizing simpler schemes relying on directly addressed PROMs. Examples of decoders using look-up tables are described in U.S. Pat. No. 4,628,298, issued to Hafle et al. on Dec. 09, 1986, U.S. Pat. No. 4,914,437, issued to Kibrick et al. on Apr. 03, 1990, and U.S. Pat. No. 4,947,166, issued to Wingate et al. on Aug. 07, 1990, each of which is hereby incorporated herein by reference in its entirety.
In every example cited herein, it is a further goal to develop from the encoded path of motion not only a series of digital logic ones and zeroes comprising the featured shift register position code, but also a standard digital quadrature signal pair as might be obtained from any conventional incremental encoder. The quadrature signal pair provides direction sensing of the motion of the reading station relative to the encoded path through standard quadrature decoding techniques employed in the decoder. Also, very importantly, it controls the spatial timing of the samples taken of the shift register code path. This ensures the strongest possible contrast between the detector signals of opposite (binary) polarities, thereby enhancing immunity to original imperfections in, contamination of, or damage to the disk or scale, to sensor/mask misalignment, and to electrical noise in the sensing circuitry.
The most commonly cited method of ensuring that the desired spatial timing is achieved by the quadrature signals is to embed a so-called timing track adjacent to the chain code track in the same substrate, either concentrically, if the encoded path of motion is arranged on a wheel, or in parallel, if the encoded path is linear or cylindrical. In every case, the timing track takes the form of a simple incremental encoder track, having nominally equal on/off duty cycle, and read by sensors positioned, or masked by displaced gratings, such that the resulting signals are offset spatially by one quarter of the incremental cycle. The period of the incremental timing track is usually selected such that a complete quadrature cycle occludes the same angle in a rotary configuration, or spans the same displacement in a linear one, as a single code bit of the chain code track. Wingate provides a very clear representation of this method in the form of an example code wheel and a description of operation which presumes the reader has a good general knowledge of conventional incremental encoding techniques.
Other alternatives have been offered in regard to the selection of the period of the incremental timing track. For example, Elms teaches a spatial timing method in which every successive quadrature transition aligns with the center of each consecutive bit position of the chain code in the adjacent track. Kibrick summarizes these arrangements, where the ratio of quadrature transitions to chain code bits is 4:1 and 1:1 respectively, and also demonstrates the theoretical validity of a 2:1 ratio as well. The logic of extrapolation suggests that whereas a practical minimum of one timing transition per chain code bit suffices to guarantee a good quality sample of each, perhaps a ratio even greater than 4:1 may be possible. In a manner of speaking, this is the case in circumstances involving absolute electronic subdivision of the quadrature cycle to augment resolution.
However, for the purpose of describing the background of the present invention, it is useful to point out that only a timing track having a period selected to provide four quadrature transitions per chain code bit has general commercial value at this time. This owes to practical considerations arising from the state of the art. For example, if the chain encoding system depends on optical principles for its embodiment, the chain code track itself is sensed by a single detector, or through a single masking aperture, whose areal dimensions are restricted to roughly those of a single code bit embedded in the track. This is not so for the incremental timing track. Since the timing track is a simple series of alternating transparent and opaque (or reflective and absorptive) markings, large area sensors can be used to view the track through a grating mask, thus generating quadrature timing signals tens or hundreds of times stronger when provided with illumination of equal intensity. This arrangement provides a fourfold increase in encoding resolution at no penalty to cost or reliability, just as it has always done with conventional incremental encoders. To coarsen the incremental timing track with respect to the indexing track serves no useful purpose. In so far as other encoding technologies relying on capacitive or inductive sensing ought to be limited by the same or similar geometric constraints as the optical ones, and may not be as amenable to analogous means of driving resolution higher by purely electronic means, this point is reinforced. It is an object of the present invention to work properly with any of the three standard ratios mentioned as well as in cooperation with known electronic resolution enhancement circuits such as are already used in conventional absolute encoders.
Based on the foregoing, a need still exists for an N bit synthesizer that can bidirectionally synthesize a pseudorandom sequence for any arbitrary encoding resolution up to and including a resolution of 2.sup.N. A further need exists for a decoder that does not use look-up tables, but instead uses the bidirectional synthesizer of the present invention. A yet further need exists for a decoder that can bidirectionally fill an accumulator with code tags using input from only one index sensor so as to easily retrofit to existing designs and still fully minimize to N bits the initialization angle or distance to be traversed when first filling the accumulator immediately after power up. Another need exists for a decoder that can keep up with contemporary encoding velocities. A yet further need exists for a decoder that works with 1:1, 2:1, or 4:1 spatial timing ratios, and also in conjunction with standard absolute resolution enhancement circuits.